1. Field of the Invention
This invention relates to pixel circuits for display systems, and more particularly relates to a frame buffer pixel circuit for a liquid crystal display.
2. Background of the Related Art
FIG. 1 shows a related art display device 10. It includes a pixel circuit display panel 20 controlled by a display control circuit 30 having a frame memory 40. The related art pixel circuit display requires a grayscale representation of more than 8 bits per color, and an operating voltage low enough to enable a battery powered display device, such as a laptop computer or a personal digital assistant (PDA). The related art pixel circuit utilizes an address driver for address selection and a scan driver for image switching and reading cycles during displaying.
FIG. 2 illustrates a related art early stage frame buffer pixel system for a liquid crystal display. Initially, a voltage proportional to the Data level is stored at the Cmem memory capacitor during data write time when the Write signal is ON. Then, the stored voltage is transferred to the Clcd capacitor when the Read signal is applied after data writing is finished. The frame buffer pixels enable a previously stored image to be displayed while new data for a new image is loading into the Cmem.
The related art frame buffer pixel circuit has various disadvantages. For example, there is a charge sharing between the Cmem memory capacitor and the Clcd capacitor, the two capacitors are shorted when the Read signal turned ON, as shown in FIGS. 3(C)-(E). The voltage levels of the Cmem memory capacitor, shown in FIG. 3(C), and the Clcd capacitor, shown in FIG. 3(E), become equal after the Read signal is applied, shown in FIG. 3(D). Hence, the capacitance of the Cmem memory capacitor has to be much larger than the capacitance of Clcd capacitor in order to minimize the charge sharing problem. However, even with a much larger Cmem memory capacitor, there is always some voltage drop due to the charge sharing effect.
Additionally, there is no charge drain at the Clcd capacitor. That is, the remaining charge at the Clcd node from the previous image interferes with the new voltage that is written for a new image. Specifically, the actual voltage level of the Clcd capacitor varies depending on the previous image voltage, as shown in FIG. 3(E).
Moreover, the Clcd capacitor is driven not by power, but is driven by the charge from the Cmem memory capacitor. Thus, the Clcd capacitor needs to be optimized first in terms of its holding time and the capacitance of the Cmem memory capacitor. Due to these disadvantages, the related art frame buffer pixel provides poor brightness and contrast ratio.
FIG. 4 illustrates a second related art frame buffer pixel circuit The frame buffer pixel utilizes gate oxide of NMOS transistor M3 as a memory capacitor. The voltage according to Data level is stored at the gate capacitor of M3 during data writing time when Write signal is ON. When the data writing is finished, the Pullup signal corresponding to Read signal is turned ON and charging the pixel electrode (e.g., Clcd capacitor). Before Pullup signal is applied, the Pulldown signal drains all charge previously stored in the pixel electrode. The charge drain of the Clcd capacitor ensures the tight voltage gets displayed, especially when the data level for the new image is lower than the previous image data level.
The simulation results of the frame buffer pixel of FIG. 4 are shown in FIG. 5. As shown in FIG. 5(E), undesired charge is induced at the pixel electrode due to the intrinsic gate capacitor of M3 which makes another path to the ground with the Clcd capacitor. These two capacitors working as a voltage divider determines the induced voltage at the Clcd capacitor during data writing time. Referring to FIG. 5, with the parameters used in the simulation, about one third of the voltage at the memory capacitor is induced during data writing time, as shown in FIGS. 5(C) and 5(E). The induced charge affects the image quality, especially the contrast ratio. To reduce the charge induction problem, the ratio of the gate capacitance Cgs to the Clcd capacitance should be increased, and the stored charge should be kept for at least one frame time. Therefore, in order to achieve a high contrast ratio, the pixel circuit requires considerable space for the gate capacitance value which is much higher than the liquid crystal display (LCD) capacitor to hold the stored voltage in most mili-second frame time applications.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.